Commit 701da0fe authored by mtufan's avatar mtufan

puae 2.3.3 ppc fixes

parent 97be08bd
...@@ -899,10 +899,12 @@ static BOOL wasFullscreen = NO; // used by ensureNotFullscreen() and restoreFull ...@@ -899,10 +899,12 @@ static BOOL wasFullscreen = NO; // used by ensureNotFullscreen() and restoreFull
if (v == tag) [menuItem setState:NSOnState]; if (v == tag) [menuItem setState:NSOnState];
else [menuItem setState:NSOffState]; else [menuItem setState:NSOffState];
#ifdef JIT
if (tag == 10) { if (tag == 10) {
if (changed_prefs.fpu_strict) [menuItem setState:NSOnState]; if (changed_prefs.fpu_strict) [menuItem setState:NSOnState];
else [menuItem setState:NSOffState]; else [menuItem setState:NSOffState];
} }
#endif
if (changed_prefs.cpu_model > 68030 || changed_prefs.cpu_compatible || changed_prefs.cpu_cycle_exact) { if (changed_prefs.cpu_model > 68030 || changed_prefs.cpu_compatible || changed_prefs.cpu_cycle_exact) {
if (tag < 3) return NO; if (tag < 3) return NO;
...@@ -1645,8 +1647,10 @@ static BOOL wasFullscreen = NO; // used by ensureNotFullscreen() and restoreFull ...@@ -1645,8 +1647,10 @@ static BOOL wasFullscreen = NO; // used by ensureNotFullscreen() and restoreFull
/* if (v == 1) v = 68881; /* if (v == 1) v = 68881;
if (v == 2) v = 68882;*/ if (v == 2) v = 68882;*/
changed_prefs.fpu_model = v; changed_prefs.fpu_model = v;
#ifdef JIT
} else { } else {
changed_prefs.fpu_strict = !changed_prefs.fpu_strict; changed_prefs.fpu_strict = !changed_prefs.fpu_strict;
#endif
} }
} }
......
...@@ -2345,6 +2345,7 @@ void gui_handle_events (void) ...@@ -2345,6 +2345,7 @@ void gui_handle_events (void)
free (gui_romname); free (gui_romname);
uae_sem_post (&gui_sem); uae_sem_post (&gui_sem);
break; break;
#ifdef SAVESTATE
case UAECMD_SAVESTATE_LOAD: case UAECMD_SAVESTATE_LOAD:
uae_sem_wait (&gui_sem); uae_sem_wait (&gui_sem);
savestate_initsave (gui_sstate_name, 0, 0, 0); savestate_initsave (gui_sstate_name, 0, 0, 0);
...@@ -2359,6 +2360,7 @@ void gui_handle_events (void) ...@@ -2359,6 +2360,7 @@ void gui_handle_events (void)
write_log ("Saved state to '%s'...\n", gui_sstate_name); write_log ("Saved state to '%s'...\n", gui_sstate_name);
uae_sem_post (&gui_sem); uae_sem_post (&gui_sem);
break; break;
#endif
/* case UAECMD_START: /* case UAECMD_START:
uae_start (); uae_start ();
break; break;
......
...@@ -64,6 +64,9 @@ ...@@ -64,6 +64,9 @@
#ifdef HAVE_SYS_STAT_H #ifdef HAVE_SYS_STAT_H
#include <sys/stat.h> #include <sys/stat.h>
#ifndef stat64
#define stat64 stat
#endif
#endif #endif
#if TIME_WITH_SYS_TIME #if TIME_WITH_SYS_TIME
......
...@@ -73,7 +73,7 @@ extern struct flag_struct regflags; ...@@ -73,7 +73,7 @@ extern struct flag_struct regflags;
#define IOR_CZNV(X) (regflags.cznv |= (X)) #define IOR_CZNV(X) (regflags.cznv |= (X))
#define SET_CZNV(X) (regflags.cznv = (X)) #define SET_CZNV(X) (regflags.cznv = (X))
#define COPY_CARRY (regflags.x = regflags.cznv) #define COPY_CARRY() (regflags.x = regflags.cznv)
/* /*
......
...@@ -31,22 +31,16 @@ ...@@ -31,22 +31,16 @@
* *
* Evaluate operand and set Z and N flags. Always clear C and V. * Evaluate operand and set Z and N flags. Always clear C and V.
*/ */
/* #define optflag_testl(v) \
#define optflag_testl (v) \
do { \ do { \
asm ( \ register uae_s32 tmp; \
__asm__ __volatile__ ( \
"cmpi cr0, %2, 0\n\t" \ "cmpi cr0, %2, 0\n\t" \
"mfcr %1\n\t" \ "mfcr %1\n\t" \
"rlwinm %0, %1, 0, 0, 3\n\t"\ "rlwinm %0, %1, 0, 0, 3\n\t"\
:: "r" (v) : "cr0" \ : "=r" (regflags.cznv), "=r" (tmp) : "r" (v) : "cr0" \
); \ ); \
} while (0) } while (0)
*/
#define optflag_testl (v) \
__asm__ __volatile__ ("cmpi cr0, %2, 0\n\t" \
"mfcr %1\n\t" \
"rlwinm %0, %1, 0, 0, 3\n\t"\
:: "r" (v) : "cr0")
#define optflag_testw(v) optflag_testl((uae_s32)(v)) #define optflag_testw(v) optflag_testl((uae_s32)(v))
#define optflag_testb(v) optflag_testl((uae_s32)(v)) #define optflag_testb(v) optflag_testl((uae_s32)(v))
...@@ -56,80 +50,51 @@ ...@@ -56,80 +50,51 @@
* *
* Perform v = s + d and set ZNCV accordingly * Perform v = s + d and set ZNCV accordingly
*/ */
/* #define optflag_addlong(v, s, d) \
#define optflag_addl(v, s, d) \
do { \
asm ( \
"addco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \
"mfcr %0\n\t" \
: "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2" DEP_XER \
); \
regflags.x = regflags.cznv; \
} while (0)
*/
#define optflag_addl(v, s, d) \
__asm__ __volatile__ ("addco. %1, %2, %3\n\t" \ __asm__ __volatile__ ("addco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \ "mcrxr cr2\n\t" \
"mfcr %0\n\t" \ "mfcr %0\n\t" \
: "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2") : "=r" (regflags.cznv), "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2" DEP_XER)
#define optflag_addw(v, s, d) do { optflag_addl((v), (s) << 16, (d) << 16); v = v >> 16; } while (0) #define optflag_addl(v, s, d) do { optflag_addlong(v, s, d); regflags.x = regflags.cznv; } while (0)
#define optflag_addb(v, s, d) do { optflag_addl((v), (s) << 24, (d) << 24); v = v >> 24; } while (0) #define optflag_addw(v, s, d) do { optflag_addlong(v, (s) << 16, (d) << 16); v = v >> 16; regflags.x = regflags.cznv; } while (0)
#define optflag_addb(v, s, d) do { optflag_addlong(v, (s) << 24, (d) << 24); v = v >> 24; regflags.x = regflags.cznv; } while (0)
/* /*
* Subtraction operations * Subtraction operations
* *
* Perform v = d - s and set ZNCV accordingly * Perform v = d - s and set ZNCV accordingly
*/ */
/*
#define optflag_subl(v, s, d) \ #define optflag_sublong(v, s, d) do { \
do { \
asm ( \
"subfco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \
"mfcr %0\n\t" \
"xoris %0,%0,32\n\t" \
: "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2" DEP_XER \
); \
regflags.x = regflags.cznv; \
} while (0)
*/
#define optflag_subl(v, s, d) do { \
__asm__ __volatile__ ("subfco. %1, %2, %3\n\t" \ __asm__ __volatile__ ("subfco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \ "mcrxr cr2\n\t" \
"mfcr %0\n\t" \ "mfcr %0\n\t" \
"xoris %0,%0,32\n\t" \ "xoris %0,%0,32\n\t" \
: "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2"); \ : "=r" (regflags.cznv), "=r" (v) : "r" (s), "r" (d) : "cr0", "cr2" DEP_XER);
regflags.x = regflags.cznv; \
} while (0)
#define optflag_subw(v, s, d) do { optflag_subl(v, (s) << 16, (d) << 16); v = v >> 16; } while (0) #define optflag_subl(v, s, d) do { optflag_sublong(v, s, d); regflags.x = regflags.cznv; } while (0)
#define optflag_subb(v, s, d) do { optflag_subl(v, (s) << 24, (d) << 24); v = v >> 24; } while (0) #define optflag_subw(v, s, d) do { optflag_sublong(v, (s) << 16, (d) << 16); v = v >> 16; regflags.x = regflags.cznv; } while (0)
#define optflag_subb(v, s, d) do { optflag_sublong(v, (s) << 24, (d) << 24); v = v >> 24; regflags.x = regflags.cznv; } while (0)
/* /*
* Compare operations * Compare operations
*/ */
/*
#define optflag_cmpl(s, d) \ #define optflag_cmplong(s, d) \
do { \ do { \
asm ( \ register uae_s32 tmp; \
__asm__ __volatile__ ( \
"subfco. %1, %2, %3\n\t" \ "subfco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \ "mcrxr cr2\n\t" \
"mfcr %0\n\t" \ "mfcr %0\n\t" \
"xoris %0,%0,32\n\t" \ "xoris %0,%0,32\n\t" \
:: "r" (s), "r" (d) : "cr0", "cr2" DEP_XER \ : "=r" (regflags.cznv), "=r" (tmp) : "r" (s), "r" (d) : "cr0", "cr2" DEP_XER \
); \ ); \
} while (0) } while (0)
*/
#define optflag_cmpl(s, d) \
__asm__ __volatile__ ("subfco. %1, %2, %3\n\t" \
"mcrxr cr2\n\t" \
"mfcr %0\n\t" \
"xoris %0,%0,32\n\t" \
:: "r" (s), "r" (d) : "cr0", "cr2")
#define optflag_cmpw(s, d) optflag_cmpl((s) << 16, (d) << 16) #define optflag_cmpl(s, d) optflag_cmplong(s, d)
#define optflag_cmpb(s, d) optflag_cmpl((s) << 24, (d) << 24) #define optflag_cmpw(s, d) optflag_cmplong((s) << 16, (d) << 16)
#define optflag_cmpb(s, d) optflag_cmplong((s) << 24, (d) << 24)
#endif /* EUAE_MACHDEP_M68KOPS_H */ #endif /* EUAE_MACHDEP_M68KOPS_H */
...@@ -54,7 +54,7 @@ static time_t fromdostime (uae_u32 dd) ...@@ -54,7 +54,7 @@ static time_t fromdostime (uae_u32 dd)
tm_local = localtime(&time_now); tm_local = localtime(&time_now);
t -= tm_local->tm_gmtoff; t -= tm_local->tm_gmtoff;
#else #else
t -= timezone; t -= (time_t)timezone;
#endif #endif
return t; return t;
} }
......
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